The present disclosure relates generally to electronic memory technology, and more specifically to sensing low voltage signals of a spin torque transfer magnetic random access memory (STT-MRAM).
STT-MRAM is an attractive emerging memory technology, offering non-volatility, high performance and high endurance. A typical STT-MRAM memory cell includes a magnetic tunnel junction (MTJ) in series with a field effect transistor (FET), which is gated by a word line (WL). A bit line (BL) and a source line (SL) run parallel to each other and perpendicular to the WL. The BL is connected to the MTJ, and the SL is connected to the FET. One memory cell along the BL is selected by turning on its WL. When a relatively large voltage (e.g., 500 mV) is forced across the cell from BL to SL, the selected cell's MTJ is written into a particular state, which is determined by the polarity of this voltage.
When the cell is in a logic “0” or parallel state, its MTJ resistance is lower than when the cell is in a logic “1” or anti-parallel state. Typical MTJ resistance values would include R0=10Ω and R1=20 KΩ. A selected cell is read by sensing the resistance from BL to SL. The “sense” or “read” voltage must be much lower than the write voltage in order to clearly distinguish write and read operations, and to avoid inadvertently disturbing the cell during a read operation. Thus, there is a need for sense amplifier (SA) designs capable of sensing very low read voltage (e.g., less than 50 mV).
However, random device variations (e.g., dimensions and other parameters) can lead to corresponding variations in R0 and R1. For very small MTJs, the actual distributions of R0 and R1 for a particular device may in practice overlap, although R1 is in theory expected to be greater than R0. In this case, it is impossible to use the same reference resistance to discriminate a logic 0 from a logic 1 for all bits. In a proposed solution, known as self-referencing, the data state resistance is sensed and stored, the cell is written to a known reference state, then the reference state resistance is sensed. Based on a change in resistance (from data to reference), or a lack thereof, the original data state can be determined.
Random device variations can also lead to variations in the threshold voltage and trans-conductance of silicon FETs, even for devices in close proximity. This effect, known generally as FET mismatch, results in random offsets in various circuits, particularly those circuits that include FET configurations such as amplifiers and comparators. Thus, FET mismatch can determine the lower limit for its read voltage. For example, using a standard amplifier/latch configuration, assume that the read voltages for logic 0 and logic 1 are 50 mV and 100 mV, respectively. In this case, the optimal voltage at the reference input of the latch is 75 mV, and the nominal signal (i.e., reference voltage minus data voltage) is approximately 25 mV, with the polarity depending on the data state. If the offset of the latch varies randomly by as much as 25 mV due to FET mismatch, there is zero margin (i.e., nominal signal minus variation) in the worst case. Increasing the read voltages would increase the margin, however the lack of margin prevents the read voltages from being lowered.
Offset-cancellation is a technique used in analog circuit designs to minimize the effects of FET mismatch. In a typical offset-cancellation technique applied to an amplifier circuit, during a first phase the amplifier offset is determined and stored on one or more capacitors. The circuit is then re-configured, and during the second phase the capacitors act to cancel out the amplifier offset, ideally resulting in zero offset. In reality, some offset still remains but has been significantly reduced.
Thus, there is a need for an STT-MRAM sensing scheme capable of reducing the impact of random device variations to thereby sense very low read voltages.